Energy-Efficient High-Speed SAR ADCs in CMOS

An ADC featuring a new architecture for an 8 b 64× interleaved CMOS ADC running at up to 100 GHz sampling frequency is presented. The ADC fulfills all specifications for 100 Gb/s ITU-OTU4 communication over long-distance optical fiber channels. It is based on a SAR ADC, known for its superior energy efficiency and suitability for deep-submicron digital CMOS processes, as the comparator is the only true analog element. Several improvements to existing SAR ADC architectures are presented. Alternate comparators are used to increase the sampling speed at no power and area penalty, and dynamic memory is used to reduce latency in the CDAC feedback. A deep-trench capacitor-based reference buffer significantly reduces power at low output impedance, and a differential CDAC with constant common mode and fractional reference voltages optimizes comparator performance and silicon area. The 64× interleaved ADC consists of a dedicated sampling and interleaving block and 64 SAR ADCs. Four interleaved passive samplers based on a sampling switch with in-line 1:4 demultiplexer provide an initial 1:16 interleaving with high linearity and more than 20 GHz input bandwidth while using only a single supply voltage

Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS

A model for voltage-based time-interleaved sampling is introduced with two implementations of highly interleaved analog-to-digital converters (ADCs) for 100 Gb/s communication systems. The model is suitable for ADCs where the analog input bandwidth is of concern and enables a tradeoff between different architectures with respect to the analog input bandwidth, the hold time of the sampled signal, and constraints on the clock path. The two ADCs at 6 and 8 b resolution implement inline demux sampling with 32× and 64× interleaving to achieve 36 GS/s at 110 mW and 90 GS/s at 667 mW, respectively. The analog input bandwidth of both ADCs exceeds 20 GHz. The SNDR of the 64× interleaved ADC is above 36 dB up to 6.1 GHz and above 33 dB up to 19.9 GHz at 90 GS/s, and the SNDR of the 32× interleaved ADC exceeds 31.6 dB up to Nyquist at 36 GS/s. The 32×and 64× interleaved ADCs are optimized for area and occupy 0.048 and 0.45 mm2, respectively, in 32 nm CMOS SOI technology

A 110mW 6 Bit 36GS/S Interleaved SAR ADC for 100 GBE Occupying 0.048mm2 in 32nm SOI CMOS

An area- and power-optimized asynchronous 32x interleaved SAR ADC achieving 36 GS/s at 110mW and 1V supply on the interleaver and 0.9V on the SAR ADCs is presented. The ADC features a 2-channel interleaver with data demultiplexing for enhanced bandwidth, a power- and area optimized binary SAR ADC, and an area optimized clocked reference buffer with a tunable constant current source. It achieves 32.6 dB SNDR up to 3GHz and 31.6 dB up to 18 GHz input frequency and 98 fJ/conversion-step with a core chip area of 340x140 um2 in 32nm SOI CMOS technology

Co-existing institutional logics and agency among top-level public servants: A praxeological approach

AbstractWhile institutional organization research to some extent has neglected the micro agency of organization members, parts of the strategy-as-practice research have tended to bracket off wider societal environments shaping the practices-in-use of top-level strategy practitioners. This article attempts to address parts of this void. This study examines the agency exerted by top-level public servants through their everyday strategy and policy work in face of co-existing logics of public administration. The findings illustrate how their action strategies span from more passive strategies of coping with coexisting logics of administration to more skilled agency of combining logics aimed at enhancing their opportunity and action space. The study suggests that the interplay between co-existing institutional logics, action strategies and the practical skills of top-level public servants provides the basis for both coping and more proactive strategies in pluralistic public administrations. Findings illustrate the role of public servants' practical sense of realizable opportunities that inform such strategies of handling co-existing institutional logics. Implications for institutional studies of organizations are outlined.</jats:p